IEEE 9.21.2023 meeting moved to Oct 5,2023: RISC-V Thunderbird SOC for HPC and AI Applications

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Doug Norton will give an overview of Austin-based InspireSemi’s disruptive next generation Thunderbird compute accelerator for HPC&AI applications. This RISC-V based “supercomputer-cluster-on-a-chip” packs 1,800 high performance CPU cores (all FP64 double-precision of their own design) onto a single SOC. For maximum/predictable performance and low latency, these CPU cores are all interconnected with their high bandwidth, low-latency mesh interconnect that can connect up to 256 of Thunderbird chips. After 3 years of customer-driven development, the chip is in final verification and will tape out at the end of September to TSMC. He will also share why the team chose to leverage the open hardware RISC-V ISA vs. other options and provide an overview of some of the many initiatives in the thriving RISC-V ecosystem.
Speaker(s): Doug Norton
6:00 to 6:05 PM – Open for participants to enter and network.
6:05 to 6:10 PM – IEEE LM and CTCN Business meeting and to introduce speaker.
6:10 to 7:30 PM – Formal Program and Q&A.

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